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| author | whitequark <whitequark@whitequark.org> | 2020-06-09 09:54:09 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-09 09:54:09 +0000 |
| commit | 74e3ac2449f521a50d5e88daa951acee1062e620 (patch) | |
| tree | f4f51475500f800019bfeea2c72a554bb4364e00 /kernel/rtlil.h | |
| parent | c172b30c24285faa2b57f84a2a5162c5f3dcfb4c (diff) | |
| parent | ef4e1594470b46eab6f311998511a5eee22a96d3 (diff) | |
| download | yosys-74e3ac2449f521a50d5e88daa951acee1062e620.tar.gz yosys-74e3ac2449f521a50d5e88daa951acee1062e620.tar.bz2 yosys-74e3ac2449f521a50d5e88daa951acee1062e620.zip | |
Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops
cxxrtl: ignore cell input signedness when it is irrelevant
Diffstat (limited to 'kernel/rtlil.h')
0 files changed, 0 insertions, 0 deletions