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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-28 19:03:18 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-28 19:03:18 +0100 |
| commit | f3a97b75c78bd6f3670445129405213c0a015481 (patch) | |
| tree | 9c39fdf8f551c153d34a088480b3bdbc97935d99 /kernel/rtlil.cc | |
| parent | 89723a45cf86a508d052dd54aa058719e314cc3c (diff) | |
| download | yosys-f3a97b75c78bd6f3670445129405213c0a015481.tar.gz yosys-f3a97b75c78bd6f3670445129405213c0a015481.tar.bz2 yosys-f3a97b75c78bd6f3670445129405213c0a015481.zip | |
Fixed performance bug in object hashing
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c262801dc..6f2d367d6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -236,7 +236,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) RTLIL::Design::Design() { - unsigned int hashidx_count = 0; + static unsigned int hashidx_count = 0; hashidx_ = hashidx_count++; refcount_modules_ = 0; @@ -450,7 +450,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const RTLIL::Module::Module() { - unsigned int hashidx_count = 0; + static unsigned int hashidx_count = 0; hashidx_ = hashidx_count++; design = nullptr; @@ -1741,7 +1741,7 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec RTLIL::Wire::Wire() { - unsigned int hashidx_count = 0; + static unsigned int hashidx_count = 0; hashidx_ = hashidx_count++; module = nullptr; @@ -1755,7 +1755,7 @@ RTLIL::Wire::Wire() RTLIL::Memory::Memory() { - unsigned int hashidx_count = 0; + static unsigned int hashidx_count = 0; hashidx_ = hashidx_count++; width = 1; @@ -1764,7 +1764,7 @@ RTLIL::Memory::Memory() RTLIL::Cell::Cell() : module(nullptr) { - unsigned int hashidx_count = 0; + static unsigned int hashidx_count = 0; hashidx_ = hashidx_count++; } |