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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:00:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:00:36 -0700 |
| commit | e612dade12b30bdee15b7dd2535af51e5ec1614d (patch) | |
| tree | e38be54476c557471cc8a30bc8c140d7c2797b3a /kernel/rtlil.cc | |
| parent | 014606affe3f1753ac16d2afd684967d72d83746 (diff) | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.tar.gz yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.tar.bz2 yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f732b56b0..502b45cfd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1381,7 +1381,34 @@ void RTLIL::Module::check() for (auto &it : processes) { log_assert(it.first == it.second->name); log_assert(!it.first.empty()); - // FIXME: More checks here.. + log_assert(it.second->root_case.compare.empty()); + std::vector<CaseRule*> all_cases = {&it.second->root_case}; + for (size_t i = 0; i < all_cases.size(); i++) { + for (auto &switch_it : all_cases[i]->switches) { + for (auto &case_it : switch_it->cases) { + for (auto &compare_it : case_it->compare) { + log_assert(switch_it->signal.size() == compare_it.size()); + } + all_cases.push_back(case_it); + } + } + } + for (auto &sync_it : it.second->syncs) { + switch (sync_it->type) { + case SyncType::ST0: + case SyncType::ST1: + case SyncType::STp: + case SyncType::STn: + case SyncType::STe: + log_assert(!sync_it->signal.empty()); + break; + case SyncType::STa: + case SyncType::STg: + case SyncType::STi: + log_assert(sync_it->signal.empty()); + break; + } + } } for (auto &it : connections_) { |