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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-30 17:00:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-30 17:00:34 +0200 |
| commit | d9d50b0b0c4da21c9bf2b0f1499297368b808491 (patch) | |
| tree | 6a926310738ae81a1b98f74066e79f423310b33b /kernel/rtlil.cc | |
| parent | 727eec04c53c6863b18883a5afd7cee1cb52a157 (diff) | |
| parent | 58e991a0eb36f0a5a23170e6818338efa7445a44 (diff) | |
| download | yosys-d9d50b0b0c4da21c9bf2b0f1499297368b808491.tar.gz yosys-d9d50b0b0c4da21c9bf2b0f1499297368b808491.tar.bz2 yosys-d9d50b0b0c4da21c9bf2b0f1499297368b808491.zip | |
Merge branch 'master' into eddie/refactor_synth_xilinx
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7e1159cac..dd6817873 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3456,7 +3456,7 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const pack(); other.pack(); - if (chunks_.size() != chunks_.size()) + if (chunks_.size() != other.chunks_.size()) return false; updhash(); |