diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
| commit | 9dc11cd842952deca8e826b662f4565e2b52bd1d (patch) | |
| tree | 6caa919ebcb4618581d8dce4a43f98dbe585bda8 /kernel/rtlil.cc | |
| parent | b25254020c7edc9e4d3fb2a24be5f029a09a1ee0 (diff) | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| download | yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.gz yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.bz2 yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9ae20a317..f6f08bb9e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -207,9 +207,12 @@ bool RTLIL::Const::is_fully_undef() const return true; } -void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id) +void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value) { - attributes[id] = RTLIL::Const(1); + if (value) + attributes[id] = RTLIL::Const(1); + else if (attributes.count(id)) + attributes.erase(id); } bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const @@ -589,7 +592,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox")) + if (selected_module(it.first) && !it.second->get_blackbox_attribute()) result.push_back(it.second); return result; } @@ -599,7 +602,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox")) + if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute()) result.push_back(it.second); return result; } @@ -609,7 +612,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (it.second->get_bool_attribute("\\blackbox")) + if (it.second->get_blackbox_attribute()) continue; else if (selected_whole_module(it.first)) result.push_back(it.second); |