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| author | David Shah <dave@ds0.me> | 2019-08-08 11:40:09 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-08-08 11:40:09 +0100 |
| commit | 83b2e0272333cfcc2529e0833723a52c066146a6 (patch) | |
| tree | 9985b7f840383419ebd5b189023ca6871a02d5a9 /kernel/rtlil.cc | |
| parent | b8cd4ad64ae9a45faecffc1a6b92a8219755bc60 (diff) | |
| parent | fb568ddb4e2ccaab352d9d062f6b4926aca75680 (diff) | |
| download | yosys-83b2e0272333cfcc2529e0833723a52c066146a6.tar.gz yosys-83b2e0272333cfcc2529e0833723a52c066146a6.tar.bz2 yosys-83b2e0272333cfcc2529e0833723a52c066146a6.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index fd98ab4bd..976772b5e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1249,6 +1249,7 @@ namespace { if (cell->type == "$_ANDNOT_") { check_gate("ABY"); return; } if (cell->type == "$_ORNOT_") { check_gate("ABY"); return; } if (cell->type == "$_MUX_") { check_gate("ABSY"); return; } + if (cell->type == "$_NMUX_") { check_gate("ABSY"); return; } if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; } if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; } if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; } @@ -1976,6 +1977,7 @@ DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y) DEF_METHOD_3(AndnotGate, "$_ANDNOT_", A, B, Y) DEF_METHOD_3(OrnotGate, "$_ORNOT_", A, B, Y) DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y) +DEF_METHOD_4(NmuxGate, "$_NMUX_", A, B, S, Y) DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y) DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y) DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y) @@ -3354,13 +3356,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - auto it = bits_.begin() + std::min<int>(offset, width_); - decltype(it) ie; - if (length >= 0) - ie = bits_.begin() + std::min<int>(offset + length, width_); - else - ie = bits_.end() + std::max<int>(length + 1, offset - width_); - return std::vector<RTLIL::SigBit>(it, ie); + return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) |