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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 17:00:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 18:44:43 -0700 |
| commit | 6b9f90de789b1d0daf93ac1d2b608b057e7ca272 (patch) | |
| tree | 5c12ac0797327a5d4387851803bf2443de5c5871 /kernel/rtlil.cc | |
| parent | fd0e3a2c43d96ba31beede9865d5000230029994 (diff) | |
| download | yosys-6b9f90de789b1d0daf93ac1d2b608b057e7ca272.tar.gz yosys-6b9f90de789b1d0daf93ac1d2b608b057e7ca272.tar.bz2 yosys-6b9f90de789b1d0daf93ac1d2b608b057e7ca272.zip | |
Fix typo
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1d380135b..f42f5430f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const { std::vector<RTLIL::Cell*> result; - result.reserve(wires_.size()); + result.reserve(cells_.size()); for (auto &it : cells_) if (design->selected(this, it.second)) result.push_back(it.second); |