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authorClifford Wolf <clifford@clifford.at>2017-08-18 11:45:15 +0200
committerClifford Wolf <clifford@clifford.at>2017-08-18 11:45:15 +0200
commit35760dd784f4b2e360a4137ce115104d1204d7a6 (patch)
treec54e9ef38bb80d410420a1e5c2b1e4f5fca81072 /kernel/rtlil.cc
parent864498527a39716a59e7531cf55bc6b8b7a1f1ed (diff)
parentd30cc60ba9148346173a1ed26f0ce833de522003 (diff)
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Merge branch 'sim'
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc33
1 files changed, 33 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 93cfef80e..4427303cc 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -161,6 +161,39 @@ std::string RTLIL::Const::decode_string() const
return string;
}
+bool RTLIL::Const::is_fully_zero() const
+{
+ cover("kernel.rtlil.const.is_fully_zero");
+
+ for (auto bit : bits)
+ if (bit != RTLIL::State::S0)
+ return false;
+
+ return true;
+}
+
+bool RTLIL::Const::is_fully_def() const
+{
+ cover("kernel.rtlil.const.is_fully_def");
+
+ for (auto bit : bits)
+ if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
+ return false;
+
+ return true;
+}
+
+bool RTLIL::Const::is_fully_undef() const
+{
+ cover("kernel.rtlil.const.is_fully_undef");
+
+ for (auto bit : bits)
+ if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
+ return false;
+
+ return true;
+}
+
void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
{
attributes[id] = RTLIL::Const(1);