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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 19:39:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 19:39:12 -0700 |
| commit | 1123c09588a6dd3964605de229c6bc4ac158b50e (patch) | |
| tree | 6f6b950cfc30c4db0963a90fe065964489fa292b /kernel/rtlil.cc | |
| parent | 18ebb86edbade4a94833dead59d69fddd980f5bd (diff) | |
| parent | d5f0794a531b36976d2c4d181b1c3921b801bbfa (diff) | |
| download | yosys-1123c09588a6dd3964605de229c6bc4ac158b50e.tar.gz yosys-1123c09588a6dd3964605de229c6bc4ac158b50e.tar.bz2 yosys-1123c09588a6dd3964605de229c6bc4ac158b50e.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f42f5430f..ded1cd60e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); @@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); |