From 1bf7a18fec76cf46a5b8710a75371e23b68d147d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Aug 2014 16:13:42 +0200
Subject: Added module->ports

---
 kernel/celltypes.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'kernel/celltypes.h')

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 6beaa3fed..5486f6acb 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -67,7 +67,8 @@ struct CellTypes
 	void setup_module(RTLIL::Module *module)
 	{
 		std::set<RTLIL::IdString> inputs, outputs;
-		for (auto wire : module->wires()) {
+		for (RTLIL::IdString wire_name : module->ports) {
+			RTLIL::Wire *wire = module->wire(wire_name);
 			if (wire->port_input)
 				inputs.insert(wire->name);
 			if (wire->port_output)
-- 
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