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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-10-08 16:52:12 -0700 |
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| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-10-08 16:52:12 -0700 |
| commit | b111ea12286b45e51fc453e3f4d7ac906e1a9f7c (patch) | |
| tree | ad9fcd28339318054214e2503518be94b936d4d3 /frontends | |
| parent | 9850de405a11fe93e4562c86be0a0830b83c2785 (diff) | |
| download | yosys-b111ea12286b45e51fc453e3f4d7ac906e1a9f7c.tar.gz yosys-b111ea12286b45e51fc453e3f4d7ac906e1a9f7c.tar.bz2 yosys-b111ea12286b45e51fc453e3f4d7ac906e1a9f7c.zip | |
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
Diffstat (limited to 'frontends')
0 files changed, 0 insertions, 0 deletions