From e936ac61ea223ca27c1b6eaf195cac66dd255602 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 4 May 2020 12:18:20 -0700 Subject: ast: swap range regardless of range_left >= 0 --- frontends/ast/simplify.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 837c14ad7..cdb7e91e0 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1079,7 +1079,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (old_range_valid != range_valid) did_something = true; - if (range_valid && range_left >= 0 && range_right > range_left) { + if (range_valid && range_right > range_left) { int tmp = range_right; range_right = range_left; range_left = tmp; -- cgit v1.2.3 From 66d0ed2bcc7195aab5b107b2536e6818fe5b244c Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 5 May 2020 04:11:16 +0000 Subject: ast/simplify: don't bitblast async ROMs declared as `logic`. Fixes #2020. --- frontends/ast/simplify.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 837c14ad7..9453937e3 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3477,8 +3477,8 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg } } - // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' - if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg)) + // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic' + if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic))) mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED; if (type == AST_MODULE && get_bool_attribute(ID::mem2reg)) -- cgit v1.2.3 From 323aa1df75dcc21e94c4dfbdb77eaad40f48d081 Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Wed, 6 May 2020 07:22:17 +0000 Subject: verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace. --- frontends/verilog/verilog_lexer.l | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index f6a3ac4db..63c0ba159 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -48,16 +48,18 @@ USING_YOSYS_NAMESPACE using namespace AST; using namespace VERILOG_FRONTEND; +#define YYSTYPE FRONTEND_VERILOG_YYSTYPE +#define YYLTYPE FRONTEND_VERILOG_YYLTYPE + YOSYS_NAMESPACE_BEGIN namespace VERILOG_FRONTEND { std::vector fn_stack; std::vector ln_stack; + YYLTYPE real_location; + YYLTYPE old_location; } YOSYS_NAMESPACE_END -#define YYSTYPE FRONTEND_VERILOG_YYSTYPE -#define YYLTYPE FRONTEND_VERILOG_YYLTYPE - #define SV_KEYWORD(_tok) \ if (sv_mode) return _tok; \ log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\ @@ -73,9 +75,6 @@ YOSYS_NAMESPACE_END #define YY_INPUT(buf,result,max_size) \ result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size) -YYLTYPE real_location; -YYLTYPE old_location; - #define YY_USER_ACTION \ old_location = real_location; \ real_location.first_line = real_location.last_line; \ -- cgit v1.2.3 From 1f3003be7d464372b1c94d6b8e47ffa0d75de0d3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 13:00:36 -0700 Subject: verilog: error out when non-ANSI task/func arguments --- frontends/verilog/verilog_parser.y | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index db9a130cf..b7c6af91e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -853,7 +853,11 @@ task_func_port: } if (astbuf2 && astbuf2->children.size() != 2) frontend_verilog_yyerror("task/function argument range must be of the form: [:], [+:], or [-:]"); - } wire_name | wire_name; + } wire_name | + { + if (!astbuf1) + frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); + } wire_name; task_func_body: task_func_body behavioral_stmt | -- cgit v1.2.3 From 237962debd9fcb7e9fb45f53bc8a53f0c34d9888 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 13 May 2020 13:33:37 -0700 Subject: verilog: default to input in sv mode if task/func has no dir ... otherwise error --- frontends/verilog/verilog_parser.y | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index b7c6af91e..f250d7685 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -855,8 +855,16 @@ task_func_port: frontend_verilog_yyerror("task/function argument range must be of the form: [:], [+:], or [-:]"); } wire_name | { - if (!astbuf1) - frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); + if (!astbuf1) { + if (!sv_mode) + frontend_verilog_yyerror("task/function argument direction missing"); + albuf = new dict; + astbuf1 = new AstNode(AST_WIRE); + current_wire_rand = false; + current_wire_const = false; + astbuf1->is_input = true; + astbuf2 = NULL; + } } wire_name; task_func_body: -- cgit v1.2.3 From 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9 Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Thu, 14 May 2020 14:38:13 +0200 Subject: Add support for non-power-of-two mem chunks in verific importer Signed-off-by: Claire Wolf --- frontends/verific/verific.cc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'frontends') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fe4bda68e..5f8a78e48 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1265,7 +1265,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->OutputSize()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) + if ((numchunks * memory->width) != int(inst->OutputSize())) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1273,6 +1273,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); + if ((numchunks & (numchunks - 1)) != 0) { + addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); + addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); + } + RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd)); cell->parameters[ID::MEMID] = memory->name.str(); @@ -1295,7 +1300,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->Input2Size()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0) + if ((numchunks * memory->width) != int(inst->Input2Size())) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1303,6 +1308,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); + if ((numchunks & (numchunks - 1)) != 0) { + addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); + addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); + } + RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr)); cell->parameters[ID::MEMID] = memory->name.str(); -- cgit v1.2.3 From 53fc3ed64563045949bcd52a03d2af586605d523 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 9 Apr 2020 14:31:14 -0700 Subject: aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created according to mergeability class, and init state as cell attr --- frontends/aiger/aigerparse.cc | 25 +++++++++++++++++++++++-- frontends/aiger/aigerparse.h | 2 +- 2 files changed, 24 insertions(+), 3 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 6fda92d73..7e5e6dd2d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -454,6 +454,14 @@ void AigerReader::parse_xaiger() for (unsigned i = 0; i < flopNum; i++) mergeability.emplace_back(parse_xaiger_literal(f)); } + else if (c == 's') { + uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + flopNum = parse_xaiger_literal(f); + log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); + initial_state.reserve(flopNum); + for (unsigned i = 0; i < flopNum; i++) + initial_state.emplace_back(parse_xaiger_literal(f)); + } else if (c == 'n') { parse_xaiger_literal(f); f >> s; @@ -767,6 +775,7 @@ void AigerReader::post_process() } } + dict mergeability_to_clock; for (uint32_t i = 0; i < flopNum; i++) { RTLIL::Wire *d = outputs[outputs.size() - flopNum + i]; log_assert(d); @@ -778,10 +787,22 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_)); + Cell* ff; + int clock_index = mergeability[i]; + if (clock_index < 0) { + ff = module->addCell(NEW_ID, ID($_DFF_N_)); + clock_index = -clock_index; + } + else if (clock_index > 0) + ff = module->addCell(NEW_ID, ID($_DFF_P_)); + else log_abort(); + auto r = mergeability_to_clock.insert(clock_index); + if (r.second) + r.first->second = module->addWire(NEW_ID); + ff->setPort(ID::C, r.first->second); ff->setPort(ID::D, d); ff->setPort(ID::Q, q); - ff->attributes[ID::abc9_mergeability] = mergeability[i]; + ff->attributes[ID::abc9_init] = initial_state[i]; } dict> wideports_cache; diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h index 46ac81212..251a24977 100644 --- a/frontends/aiger/aigerparse.h +++ b/frontends/aiger/aigerparse.h @@ -45,7 +45,7 @@ struct AigerReader std::vector outputs; std::vector bad_properties; std::vector boxes; - std::vector mergeability; + std::vector mergeability, initial_state; AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports); void parse_aiger(); -- cgit v1.2.3 From 483a190c1b468b2a22fe7f2b92075953c6095f7d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 13 Apr 2020 13:11:25 -0700 Subject: aiger: -xaiger to parse initial state back into (* init *) on Q wire --- frontends/aiger/aigerparse.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7e5e6dd2d..ed3a926c6 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -802,7 +802,8 @@ void AigerReader::post_process() ff->setPort(ID::C, r.first->second); ff->setPort(ID::D, d); ff->setPort(ID::Q, q); - ff->attributes[ID::abc9_init] = initial_state[i]; + log_assert(GetSize(q) == 1); + q->attributes[ID::init] = initial_state[i]; } dict> wideports_cache; -- cgit v1.2.3 From 6f4f795953b2a38ec77984c7e1b50f579b59272e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 15 Apr 2020 12:15:36 -0700 Subject: aiger/xaiger: use odd for negedge clk, even for posedge Since abc9 doesn't like negative mergeability values --- frontends/aiger/aigerparse.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index ed3a926c6..16e94c394 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -789,13 +789,12 @@ void AigerReader::post_process() Cell* ff; int clock_index = mergeability[i]; - if (clock_index < 0) { + if (clock_index & 1) { ff = module->addCell(NEW_ID, ID($_DFF_N_)); - clock_index = -clock_index; + clock_index--; } - else if (clock_index > 0) + else ff = module->addCell(NEW_ID, ID($_DFF_P_)); - else log_abort(); auto r = mergeability_to_clock.insert(clock_index); if (r.second) r.first->second = module->addWire(NEW_ID); -- cgit v1.2.3 From 4017cc6380c3b13f416e55e4e65cf98e7caf45e1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 14:01:54 -0700 Subject: aiger: -xaiger to return $_FF_ flops --- frontends/aiger/aigerparse.cc | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) (limited to 'frontends') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 16e94c394..d25587e48 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -787,21 +787,8 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - Cell* ff; - int clock_index = mergeability[i]; - if (clock_index & 1) { - ff = module->addCell(NEW_ID, ID($_DFF_N_)); - clock_index--; - } - else - ff = module->addCell(NEW_ID, ID($_DFF_P_)); - auto r = mergeability_to_clock.insert(clock_index); - if (r.second) - r.first->second = module->addWire(NEW_ID); - ff->setPort(ID::C, r.first->second); - ff->setPort(ID::D, d); - ff->setPort(ID::Q, q); - log_assert(GetSize(q) == 1); + Cell* ff = module->addFfGate(NEW_ID, d, q); + ff->attributes[ID::abc9_mergeability] = mergeability[i]; q->attributes[ID::init] = initial_state[i]; } -- cgit v1.2.3 From 7101ef550ba4b215d41fc82e52e3aa714afcbdbe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 16:10:11 -0700 Subject: verilog: attributes before task enable (but 13 s/r conflicts) --- frontends/verilog/verilog_parser.y | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index db9a130cf..fd4ff68a9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2217,23 +2217,23 @@ behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | simple_behavioral_stmt ';' | ';' | - hierarchical_id attr { + attr hierarchical_id { AstNode *node = new AstNode(AST_TCALL); - node->str = *$1; - delete $1; + node->str = *$2; + delete $2; ast_stack.back()->children.push_back(node); ast_stack.push_back(node); - append_attr(node, $2); + append_attr(node, $1); } opt_arg_list ';'{ ast_stack.pop_back(); } | - TOK_MSG_TASKS attr { + attr TOK_MSG_TASKS { AstNode *node = new AstNode(AST_TCALL); - node->str = *$1; - delete $1; + node->str = *$2; + delete $2; ast_stack.back()->children.push_back(node); ast_stack.push_back(node); - append_attr(node, $2); + append_attr(node, $1); } opt_arg_list ';'{ ast_stack.pop_back(); } | @@ -2330,8 +2330,6 @@ behavioral_stmt: ast_stack.pop_back(); }; - ; - unique_case_attr: /* empty */ { $$ = false; -- cgit v1.2.3 From fa8cb3e35da68ceb55a9147bc1faacf68ad8bbfa Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Sun, 17 May 2020 11:31:11 +0200 Subject: Revert "Add support for non-power-of-two mem chunks in verific importer" This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9. --- frontends/verific/verific.cc | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) (limited to 'frontends') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5f8a78e48..fe4bda68e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1265,7 +1265,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->OutputSize()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->OutputSize())) + if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1273,11 +1273,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); - if ((numchunks & (numchunks - 1)) != 0) { - addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); - addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); - } - RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd)); cell->parameters[ID::MEMID] = memory->name.str(); @@ -1300,7 +1295,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->Input2Size()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->Input2Size())) + if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0) log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); for (int i = 0; i < numchunks; i++) @@ -1308,11 +1303,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); - if ((numchunks & (numchunks - 1)) != 0) { - addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks)); - addr = module->Add(NEW_ID, addr, RTLIL::Const(i)); - } - RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr)); cell->parameters[ID::MEMID] = memory->name.str(); -- cgit v1.2.3 From aee439360bba642dcbffe5b803aa9a994b11d183 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Mon, 18 May 2020 18:15:03 +0200 Subject: Add force_downto and force_upto wire attributes. Fixes #2058. --- frontends/ast/genrtlil.cc | 2 +- frontends/ast/simplify.cc | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d4e9baa5f..cdc3adc9c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1055,7 +1055,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!range_valid) log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str()); - if (!(range_left >= range_right || (range_left == -1 && range_right == 0))) + if (!(range_left + 1 >= range_right)) log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index f629df387..3314819fb 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1098,6 +1098,25 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_swapped = children[0]->range_swapped; range_left = children[0]->range_left; range_right = children[0]->range_right; + bool force_upto = false, force_downto = false; + if (attributes.count(ID::force_upto)) { + AstNode *val = attributes[ID::force_upto]; + if (val->type != AST_CONSTANT) + log_file_error(filename, location.first_line, "Attribute `force_upto' with non-constant value!\n"); + force_upto = val->asAttrConst().as_bool(); + } + if (attributes.count(ID::force_downto)) { + AstNode *val = attributes[ID::force_downto]; + if (val->type != AST_CONSTANT) + log_file_error(filename, location.first_line, "Attribute `force_downto' with non-constant value!\n"); + force_downto = val->asAttrConst().as_bool(); + } + if (force_upto && force_downto) + log_file_error(filename, location.first_line, "Attributes `force_downto' and `force_upto' cannot be both set!\n"); + if ((force_upto && !range_swapped) || (force_downto && range_swapped)) { + std::swap(range_left, range_right); + range_swapped = force_upto; + } } } else { if (!range_valid) -- cgit v1.2.3 From 38e858af8d5f61677d9686c022c864857f729d58 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 May 2020 09:10:56 -0700 Subject: Update frontends/verilog/verilog_parser.y Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index fd4ff68a9..ae7a3f4aa 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2216,7 +2216,7 @@ simple_behavioral_stmt: behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | - simple_behavioral_stmt ';' | ';' | + attr simple_behavioral_stmt ';' | ';' | attr hierarchical_id { AstNode *node = new AstNode(AST_TCALL); node->str = *$2; -- cgit v1.2.3 From d21a07c7b5ef57de5428e5f7913338af582146b5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 09:33:19 -0700 Subject: verilog: fix #2037 by permitting (and freeing) attributes on null stmt --- frontends/verilog/verilog_parser.y | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d39b72547..a0250439e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2228,7 +2228,11 @@ simple_behavioral_stmt: behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | - attr simple_behavioral_stmt ';' | ';' | + attr simple_behavioral_stmt ';' | + attr ';' { + log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); + free_attr($1); + } | attr hierarchical_id { AstNode *node = new AstNode(AST_TCALL); node->str = *$2; -- cgit v1.2.3 From 88bddb37c91e8fe136e5c9cc2ade20fadccd1946 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 10:20:33 -0700 Subject: verilog: handle empty generate statement by removing gen_stmt_or_null... ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay. --- frontends/verilog/verilog_parser.y | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index a0250439e..eb7e136ae 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2440,7 +2440,7 @@ gen_case_item: } case_select { case_type_stack.push_back(0); SET_AST_NODE_LOC(ast_stack.back(), @2, @2); - } gen_stmt_or_null { + } gen_stmt_block { case_type_stack.pop_back(); ast_stack.pop_back(); }; @@ -2532,7 +2532,11 @@ module_gen_body: /* empty */; gen_stmt_or_module_body_stmt: - gen_stmt | module_body_stmt; + gen_stmt | module_body_stmt | + attr ';' { + log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); + free_attr($1); + }; // this production creates the obligatory if-else shift/reduce conflict gen_stmt: @@ -2554,7 +2558,7 @@ gen_stmt: AstNode *block = new AstNode(AST_GENBLOCK); ast_stack.back()->children.push_back(block); ast_stack.push_back(block); - } gen_stmt_or_null { + } gen_stmt_block { ast_stack.pop_back(); } opt_gen_else { SET_AST_NODE_LOC(ast_stack.back(), @1, @7); @@ -2604,11 +2608,8 @@ gen_stmt_block: ast_stack.pop_back(); }; -gen_stmt_or_null: - gen_stmt_block | ';'; - opt_gen_else: - TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN; + TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN; expr: basic_expr { -- cgit v1.2.3 From 1c117ac0236517d0d7150dcc8d1fed19288bd692 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 10:46:40 -0700 Subject: verilog: do not warn for attributes on null statements --- frontends/verilog/verilog_parser.y | 2 -- 1 file changed, 2 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index eb7e136ae..475557af9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2230,7 +2230,6 @@ behavioral_stmt: non_opt_delay behavioral_stmt | attr simple_behavioral_stmt ';' | attr ';' { - log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); free_attr($1); } | attr hierarchical_id { @@ -2534,7 +2533,6 @@ module_gen_body: gen_stmt_or_module_body_stmt: gen_stmt | module_body_stmt | attr ';' { - log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n"); free_attr($1); }; -- cgit v1.2.3 From c5a9abba11a2e69a5e9944c179f7dba3d24f417a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 May 2020 09:46:26 -0700 Subject: verilog: move attr from simple_behav_stmt to its children to attach --- frontends/verilog/verilog_parser.y | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 475557af9..c8223f41d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2203,32 +2203,36 @@ assert_property: }; simple_behavioral_stmt: - lvalue '=' delay expr { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4); + attr lvalue '=' delay expr { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @4); + SET_AST_NODE_LOC(node, @2, @5); + append_attr(node, $1); } | - lvalue TOK_INCREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true))); + attr lvalue TOK_INCREMENT { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true))); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @2); + SET_AST_NODE_LOC(node, @2, @3); + append_attr(node, $1); } | - lvalue TOK_DECREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true))); + attr lvalue TOK_DECREMENT { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true))); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @2); + SET_AST_NODE_LOC(node, @2, @3); + append_attr(node, $1); } | - lvalue OP_LE delay expr { - AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4); + attr lvalue OP_LE delay expr { + AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5); ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @1, @4); + SET_AST_NODE_LOC(node, @2, @5); + append_attr(node, $1); }; // this production creates the obligatory if-else shift/reduce conflict behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | - attr simple_behavioral_stmt ';' | + simple_behavioral_stmt ';' | attr ';' { free_attr($1); } | -- cgit v1.2.3 From 6aa0f72ae9e47c81441a2cecef18b7f90671ec6d Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Fri, 22 May 2020 14:29:42 +0100 Subject: Silence spurious warning in Verilog lexer when compiling with GCC The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL. --- frontends/verilog/verilog_lexer.l | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index f6a3ac4db..65a2e9a78 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -128,7 +128,9 @@ static bool isUserType(std::string &s) %x BASED_CONST %% - int comment_caller; + // Initialise comment_caller to something to avoid a "maybe undefined" + // warning from GCC. + int comment_caller = INITIAL; "`file_push "[^\n]* { fn_stack.push_back(current_filename); -- cgit v1.2.3 From 13b2963dedebf86129574192b0d4719956e93d82 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 18 May 2020 03:18:42 +0000 Subject: ilang_lexer: fix check for out of range literal. Commit ca70a104 did not use a correct check. --- frontends/ilang/ilang_lexer.l | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'frontends') diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l index 62f53d18e..3362ed641 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/ilang/ilang_lexer.l @@ -91,8 +91,10 @@ USING_YOSYS_NAMESPACE [0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; } -?[0-9]+ { char *end = nullptr; + errno = 0; long value = strtol(yytext, &end, 10); - if (end != yytext + strlen(yytext)) + log_assert(end == yytext + strlen(yytext)); + if (errno == ERANGE) return TOK_INVALID; // literal out of range of long if (value < INT_MIN || value > INT_MAX) return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms) -- cgit v1.2.3 From 71072d1945b76107a4adc84f6666d100beca6ced Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 1 Jun 2020 10:30:03 +0200 Subject: Support asymmetric memories for verific frontend --- frontends/verific/verific.cc | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'frontends') diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fe4bda68e..cb0368fd5 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -974,6 +974,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->memories[memory->name] = memory; int number_of_bits = net->Size(); + number_of_bits = 1 << ceil_log2(number_of_bits); int bits_in_word = number_of_bits; FOREACH_PORTREF_OF_NET(net, si, pr) { if (pr->GetInst()->Type() == OPER_READ_PORT) { @@ -1265,9 +1266,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->OutputSize()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) - log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); - for (int i = 0; i < numchunks; i++) { RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; @@ -1295,9 +1293,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->Input2Size()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0) - log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); - for (int i = 0; i < numchunks; i++) { RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; -- cgit v1.2.3