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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 03:17:35 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 03:41:53 +0200 |
| commit | 7f1789ad1bb978132e8e09fee54ded81b370fcb3 (patch) | |
| tree | 9d83b8a9f3ccd70418086bd17ec237e9dc1f5775 /frontends/vhdl2verilog | |
| parent | cd699254377b08729342026056f97d9d6bc1e2f3 (diff) | |
| download | yosys-7f1789ad1bb978132e8e09fee54ded81b370fcb3.tar.gz yosys-7f1789ad1bb978132e8e09fee54ded81b370fcb3.tar.bz2 yosys-7f1789ad1bb978132e8e09fee54ded81b370fcb3.zip | |
Fixed typo in cover id
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions