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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-04 15:33:51 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-04 15:40:08 +0200 |
| commit | 0bb694221832f250977437f29365bc5e17c4cd09 (patch) | |
| tree | 593de0bdf37af0772c69424eccc9dbdd2dc538d1 /frontends/vhdl2verilog/Makefile.inc | |
| parent | b5a3419ac2c6f367b90f062c4e2252029910cdb9 (diff) | |
| download | yosys-0bb694221832f250977437f29365bc5e17c4cd09.tar.gz yosys-0bb694221832f250977437f29365bc5e17c4cd09.tar.bz2 yosys-0bb694221832f250977437f29365bc5e17c4cd09.zip | |
Added "show -signed"
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