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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-04 15:19:24 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-04 15:40:07 +0200 |
| commit | b5a3419ac2c6f367b90f062c4e2252029910cdb9 (patch) | |
| tree | bbc318d91ef1f5b8ba1117b3f317cce007236d0b /frontends/vhdl2verilog/Makefile.inc | |
| parent | ebbbe7fc8360ca0bd8f840d3df1b77ab2fb569b6 (diff) | |
| download | yosys-b5a3419ac2c6f367b90f062c4e2252029910cdb9.tar.gz yosys-b5a3419ac2c6f367b90f062c4e2252029910cdb9.tar.bz2 yosys-b5a3419ac2c6f367b90f062c4e2252029910cdb9.zip | |
Added support for non-standard "module mod_name(...);" syntax
Diffstat (limited to 'frontends/vhdl2verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions