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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-19 20:31:53 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-19 20:31:53 +0100 |
| commit | 8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5 (patch) | |
| tree | e24d5d241672cbaddf17fce33f5429392014e5e9 /frontends/verilog | |
| parent | a7ac8393d47303aa3f2bbd103dfde1ec32e12941 (diff) | |
| parent | fe1fb1336b44bb073125aa4b42f12baa316e9fea (diff) | |
| download | yosys-8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5.tar.gz yosys-8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5.tar.bz2 yosys-8c0740bcf7a1149ac11332f7e7fd9c8f78f0a0b5.zip | |
Merge pull request #885 from YosysHQ/clifford/fix873
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Diffstat (limited to 'frontends/verilog')
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