From 81d4e9e7c1c311f837dadb1634c83b4e70929669 Mon Sep 17 00:00:00 2001
From: Andrew Becker <andrew.becker@epfl.ch>
Date: Mon, 14 Mar 2016 19:28:34 +0100
Subject: Use left-recursive rule for cell_port_list in Verilog parser.

---
 frontends/verilog/verilog_parser.y | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

(limited to 'frontends/verilog/verilog_parser.y')

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 863fee599..7849757ec 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -801,14 +801,14 @@ single_cell:
 			astbuf2->str = *$1;
 		delete $1;
 		ast_stack.back()->children.push_back(astbuf2);
-	} '(' cell_port_list ')' |
+	} '(' cell_port_list_opt ')' |
 	TOK_ID non_opt_range {
 		astbuf2 = astbuf1->clone();
 		if (astbuf2->type != AST_PRIMITIVE)
 			astbuf2->str = *$1;
 		delete $1;
 		ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2));
-	} '(' cell_port_list ')';
+	} '(' cell_port_list_opt ')';
 
 prim_list:
 	single_prim |
@@ -819,7 +819,7 @@ single_prim:
 	/* no name */ {
 		astbuf2 = astbuf1->clone();
 		ast_stack.back()->children.push_back(astbuf2);
-	} '(' cell_port_list ')';
+	} '(' cell_port_list_opt ')';
 
 cell_parameter_list_opt:
 	'#' '(' cell_parameter_list ')' | /* empty */;
@@ -842,14 +842,18 @@ cell_parameter:
 		delete $2;
 	};
 
-cell_port_list:
-	/* empty */ | cell_port |
-	cell_port ',' cell_port_list |
+cell_port_list_opt:
+	/* empty */ |
+	cell_port_list |
 	/* empty */ ',' {
 		AstNode *node = new AstNode(AST_ARGUMENT);
 		astbuf2->children.push_back(node);
 	} cell_port_list;
 
+cell_port_list:
+	cell_port |
+	cell_port_list ',' cell_port;
+
 cell_port:
 	expr {
 		AstNode *node = new AstNode(AST_ARGUMENT);
-- 
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