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author | Clifford Wolf <clifford@clifford.at> | 2018-09-24 20:51:16 +0200 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-10-08 11:38:10 -0700 |
commit | 89ef6600bcc0a52c3ce2f22805fd877b7528e8d6 (patch) | |
tree | ba05f2a1cc9f733be726ef65ccd639466ee297f0 /frontends/verilog/verilog_frontend.cc | |
parent | e8431d1508ff28bf8983d7f2f1859060c9d9fdcd (diff) | |
download | yosys-89ef6600bcc0a52c3ce2f22805fd877b7528e8d6.tar.gz yosys-89ef6600bcc0a52c3ce2f22805fd877b7528e8d6.tar.bz2 yosys-89ef6600bcc0a52c3ce2f22805fd877b7528e8d6.zip |
Add "read_verilog -noassert -noassume -assert-assumes"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
-rw-r--r-- | frontends/verilog/verilog_frontend.cc | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 8dcc7c5aa..aeea36a2b 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -66,12 +66,21 @@ struct VerilogFrontend : public Frontend { log(" enable support for SystemVerilog assertions and some Yosys extensions\n"); log(" replace the implicit -D SYNTHESIS with -D FORMAL\n"); log("\n"); + log(" -noassert\n"); + log(" ignore assert() statements\n"); + log("\n"); + log(" -noassume\n"); + log(" ignore assume() statements\n"); + log("\n"); log(" -norestrict\n"); - log(" ignore restrict() assertions\n"); + log(" ignore restrict() statements\n"); log("\n"); log(" -assume-asserts\n"); log(" treat all assert() statements like assume() statements\n"); log("\n"); + log(" -assert-assumes\n"); + log(" treat all assume() statements like assert() statements\n"); + log("\n"); log(" -dump_ast1\n"); log(" dump abstract syntax tree (before simplification)\n"); log("\n"); @@ -229,6 +238,14 @@ struct VerilogFrontend : public Frontend { formal_mode = true; continue; } + if (arg == "-noassert") { + noassert_mode = true; + continue; + } + if (arg == "-noassume") { + noassume_mode = true; + continue; + } if (arg == "-norestrict") { norestrict_mode = true; continue; @@ -237,6 +254,10 @@ struct VerilogFrontend : public Frontend { assume_asserts_mode = true; continue; } + if (arg == "-assert-assumes") { + assert_assumes_mode = true; + continue; + } if (arg == "-dump_ast1") { flag_dump_ast1 = true; continue; |