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| author | Clifford Wolf <clifford@clifford.at> | 2018-09-23 10:32:54 +0200 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2018-10-08 11:38:10 -0700 |
| commit | e8431d1508ff28bf8983d7f2f1859060c9d9fdcd (patch) | |
| tree | f7d7c63ef13ce3d9af9a87fdd86f3e95ffa89c19 /frontends/verilog/verilog_frontend.cc | |
| parent | a9085ff4af005f59d22403047ea7b3e0e7453ffd (diff) | |
| download | yosys-e8431d1508ff28bf8983d7f2f1859060c9d9fdcd.tar.gz yosys-e8431d1508ff28bf8983d7f2f1859060c9d9fdcd.tar.bz2 yosys-e8431d1508ff28bf8983d7f2f1859060c9d9fdcd.zip | |
Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
0 files changed, 0 insertions, 0 deletions