From c96eb2fbd7cb2f4838350c02baf3e4b23c4b2ad2 Mon Sep 17 00:00:00 2001
From: Diego H <diego@yosyshq.com>
Date: Thu, 4 Feb 2021 15:35:35 -0600
Subject: Accept disable case for SVA liveness properties.

---
 frontends/verific/verificsva.cc | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'frontends/verific')

diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 632043b6f..1f5da1b1d 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1759,6 +1759,11 @@ struct VerificSvaImporter
 						clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
 					}
 
+					// accept in disable case
+
+					if (clocking.disable_sig != State::S0)
+						sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig);
+
 					// generate fair/live cell
 
 					RTLIL::Cell *c = nullptr;
-- 
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