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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-02-08 09:22:48 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2023-02-08 09:22:48 +0100 |
| commit | 109b88c3791c87e819fb5a6c3c52f964655fd379 (patch) | |
| tree | c2a53e73a48dadb701c73ab0e97cbb515a64ee33 /frontends/verific/verific.h | |
| parent | e7e37df91b6e24ff76009179e568de33ad317a00 (diff) | |
| download | yosys-109b88c3791c87e819fb5a6c3c52f964655fd379.tar.gz yosys-109b88c3791c87e819fb5a6c3c52f964655fd379.tar.bz2 yosys-109b88c3791c87e819fb5a6c3c52f964655fd379.zip | |
For case select values use Sa instead of Sx and Sz
Diffstat (limited to 'frontends/verific/verific.h')
| -rw-r--r-- | frontends/verific/verific.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index d9f0077db..44485751c 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -87,6 +87,7 @@ struct VerificImporter RTLIL::SigSpec operatorInput1(Verific::Instance *inst); RTLIL::SigSpec operatorInput2(Verific::Instance *inst); RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname); + RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname); RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr); bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name); |