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author | Clifford Wolf <clifford@clifford.at> | 2018-06-28 23:58:15 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2018-06-28 23:58:15 +0200 |
commit | afedb2d03ee07738025ae77d73d280044c29ec2f (patch) | |
tree | b463682df4d9424a5328f8ea75c0bd7488ac5c5c /frontends/verific/verific.cc | |
parent | 07e616900c2d6ddf021644f9687954d92ac8109a (diff) | |
download | yosys-afedb2d03ee07738025ae77d73d280044c29ec2f.tar.gz yosys-afedb2d03ee07738025ae77d73d280044c29ec2f.tar.bz2 yosys-afedb2d03ee07738025ae77d73d280044c29ec2f.zip |
Add "read -sv -D" support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific/verific.cc')
-rw-r--r-- | frontends/verific/verific.cc | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 4fa74df3d..c9a071f70 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1693,6 +1693,9 @@ struct VerificPass : public Pass { log("Files passed to different calls to this command are treated as belonging to\n"); log("different compilation units.\n"); log("\n"); + log("Additional -D<macro>[=<value>] options may be added after the option indicating\n"); + log("the language version (and before file names) to set additional verilog defines.\n"); + log("\n"); log("\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n"); log("\n"); @@ -1860,8 +1863,25 @@ struct VerificPass : public Pass { else log_abort(); - for (argidx++; argidx < GetSize(args); argidx++) - file_names.Insert(args[argidx].c_str()); + for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].substr(0, 2) == "-D"; argidx++) { + std::string name = args[argidx].substr(2); + if (args[argidx] == "-D") { + if (++argidx >= GetSize(args)) + break; + name = args[argidx]; + } + size_t equal = name.find('='); + if (equal != std::string::npos) { + string value = name.substr(equal+1); + name = name.substr(0, equal); + veri_file::DefineMacro(name.c_str(), value.c_str()); + } else { + veri_file::DefineMacro(name.c_str()); + } + } + + while (argidx < GetSize(args)) + file_names.Insert(args[argidx++].c_str()); if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU)) log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); @@ -2142,6 +2162,9 @@ struct ReadPass : public Pass { log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n"); log("is only available via Verific.)\n"); log("\n"); + log("Additional -D<macro>[=<value>] options may be added after the option indicating\n"); + log("the language version (and before file names) to set additional verilog defines.\n"); + log("\n"); log("\n"); log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n"); log("\n"); |