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authorClifford Wolf <clifford@clifford.at>2018-06-28 23:43:38 +0200
committerClifford Wolf <clifford@clifford.at>2018-06-28 23:43:38 +0200
commit07e616900c2d6ddf021644f9687954d92ac8109a (patch)
treebc7a040dfbc5276741dc408bf16d688848d40f31 /frontends/verific/verific.cc
parentfe2ee833e154691ef61cc72833b86e02266039a2 (diff)
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Add "read -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific/verific.cc')
-rw-r--r--frontends/verific/verific.cc32
1 files changed, 32 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index fb27810dd..4fa74df3d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1715,6 +1715,11 @@ struct VerificPass : public Pass {
log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
log("\n");
log("\n");
+ log(" verific -vlog-undef <macro>..\n");
+ log("\n");
+ log("Remove Verilog defines previously set with -vlog-define.\n");
+ log("\n");
+ log("\n");
log(" verific -import [options] <top-module>..\n");
log("\n");
log("Elaborate the design for the specified top modules, import to Yosys and\n");
@@ -1828,6 +1833,14 @@ struct VerificPass : public Pass {
goto check_error;
}
+ if (GetSize(args) > argidx && args[argidx] == "-vlog-undef") {
+ for (argidx++; argidx < GetSize(args); argidx++) {
+ string name = args[argidx];
+ veri_file::UndefineMacro(name.c_str());
+ }
+ goto check_error;
+ }
+
if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv"))
{
@@ -2139,6 +2152,11 @@ struct ReadPass : public Pass {
log("\n");
log("Set global Verilog/SystemVerilog defines.\n");
log("\n");
+ log("\n");
+ log(" read -undef <macro>..\n");
+ log("\n");
+ log("Unset global Verilog/SystemVerilog defines.\n");
+ log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
@@ -2200,6 +2218,20 @@ struct ReadPass : public Pass {
return;
}
+ if (args[1] == "-undef") {
+ if (use_verific) {
+ args[0] = "verific";
+ args[1] = "-vlog-undef";
+ Pass::call(design, args);
+ }
+ args[0] = "verilog_defines";
+ args.erase(args.begin()+1, args.begin()+2);
+ for (int i = 1; i < GetSize(args); i++)
+ args[i] = "-U" + args[i];
+ Pass::call(design, args);
+ return;
+ }
+
log_cmd_error("Missing or unsupported mode parameter.\n");
}
} ReadPass;