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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 14:05:38 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-15 14:05:38 +0200 |
| commit | 67b10262975340e0b53f8d1072ac2e1c1f087fb1 (patch) | |
| tree | c10a6e56f6f5b61ce3fbff7c165207cc40d704c8 /frontends/verific/verific.cc | |
| parent | d8e40c75eb96e7f3c995b2acd018b5cba6005cdd (diff) | |
| parent | 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc (diff) | |
| download | yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.gz yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.bz2 yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.zip | |
Merge pull request #591 from hzeller/virtual-override
Consistent use of 'override' for virtual methods in derived classes.
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b8dd72b98..e993eb740 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1685,7 +1685,7 @@ bool check_noverific_env() struct VerificPass : public Pass { VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1784,7 +1784,7 @@ struct VerificPass : public Pass { log("\n"); } #ifdef YOSYS_ENABLE_VERIFIC - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n"); @@ -2165,7 +2165,7 @@ struct VerificPass : public Pass { } #else /* YOSYS_ENABLE_VERIFIC */ - virtual void execute(std::vector<std::string>, RTLIL::Design *) { + void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE { log_cmd_error("This version of Yosys is built without Verific support.\n"); } #endif @@ -2173,7 +2173,7 @@ struct VerificPass : public Pass { struct ReadPass : public Pass { ReadPass() : Pass("read", "load HDL designs") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2206,7 +2206,7 @@ struct ReadPass : public Pass { log("Add directory to global Verilog/SystemVerilog include directories.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing mode parameter.\n"); |