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authorHenner Zeller <h.zeller@acm.org>2018-07-20 23:41:18 -0700
committerHenner Zeller <h.zeller@acm.org>2018-07-20 23:51:06 -0700
commit3aa4484a3cd9a2e82fddd499cde575eaf8c565cc (patch)
tree39d2caa1122c32a56231ecd99fe3364721b53c3c /frontends/verific/verific.cc
parent323f6f6f6006eadcaec180f2cc1556f1f3303be3 (diff)
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Consistent use of 'override' for virtual methods in derived classes.
o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
Diffstat (limited to 'frontends/verific/verific.cc')
-rw-r--r--frontends/verific/verific.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 8937cdde8..09bb253f5 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1685,7 +1685,7 @@ bool check_noverific_env()
struct VerificPass : public Pass {
VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1784,7 +1784,7 @@ struct VerificPass : public Pass {
log("\n");
}
#ifdef YOSYS_ENABLE_VERIFIC
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
if (check_noverific_env())
log_cmd_error("This version of Yosys is built without Verific support.\n");
@@ -2162,7 +2162,7 @@ struct VerificPass : public Pass {
}
#else /* YOSYS_ENABLE_VERIFIC */
- virtual void execute(std::vector<std::string>, RTLIL::Design *) {
+ void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE {
log_cmd_error("This version of Yosys is built without Verific support.\n");
}
#endif
@@ -2170,7 +2170,7 @@ struct VerificPass : public Pass {
struct ReadPass : public Pass {
ReadPass() : Pass("read", "load HDL designs") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -2203,7 +2203,7 @@ struct ReadPass : public Pass {
log("Add directory to global Verilog/SystemVerilog include directories.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
if (args.size() < 2)
log_cmd_error("Missing mode parameter.\n");