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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
| commit | 0bc95f1e049afc35bb5ea30663b0a5725dfbf584 (patch) | |
| tree | 3a8641d3a9bb5794a24145ce368f3db7a3963709 /frontends/verific/verific.cc | |
| parent | 1565d1af69f552b790aa43fd6be194ee59ab76f3 (diff) | |
| download | yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.gz yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.bz2 yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.zip | |
Added "yosys -D" feature
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b0fdedccd..7dd36a747 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -850,7 +850,7 @@ struct VerificPass : public Pass { #ifdef YOSYS_ENABLE_VERIFIC virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n"); + log_header(design, "Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n"); Message::SetConsoleOutput(0); Message::RegisterCallBackMsg(msg_func); |