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authorMarcelina Koƛcielnicka <mwk@0x04.net>2021-07-11 23:57:53 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-07-12 00:47:34 +0200
commit009940f56ca71cc8655a13a514371eb5757b96ca (patch)
tree8b194a81a92590973eb662c1207a876d010b2966 /frontends/rtlil
parent726fabd65e51c7a15a2a2dc24d3b99426ef43ad2 (diff)
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rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
Diffstat (limited to 'frontends/rtlil')
-rw-r--r--frontends/rtlil/rtlil_parser.y4
1 files changed, 1 insertions, 3 deletions
diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y
index 0e6eacf88..67aeb10e0 100644
--- a/frontends/rtlil/rtlil_parser.y
+++ b/frontends/rtlil/rtlil_parser.y
@@ -283,10 +283,8 @@ proc_stmt:
TOK_PROCESS TOK_ID EOL {
if (current_module->processes.count($2) != 0)
rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of process %s.", $2).c_str());
- current_process = new RTLIL::Process;
- current_process->name = $2;
+ current_process = current_module->addProcess($2);
current_process->attributes = attrbuf;
- current_module->processes[$2] = current_process;
switch_stack.clear();
switch_stack.push_back(&current_process->root_case.switches);
case_stack.clear();