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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 12:03:39 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 12:03:39 +0200 |
| commit | c989adcc2d466bb3e2e83cf67ad0a193f6628fa6 (patch) | |
| tree | f3d830e5481ae9e578f2915bc1bdd9dc518595f4 /frontends/rtlil/rtlil_lexer.l | |
| parent | 75032a565d22506ae7910bfa00e2b71558a30e26 (diff) | |
| download | yosys-c989adcc2d466bb3e2e83cf67ad0a193f6628fa6.tar.gz yosys-c989adcc2d466bb3e2e83cf67ad0a193f6628fa6.tar.bz2 yosys-c989adcc2d466bb3e2e83cf67ad0a193f6628fa6.zip | |
If not multiclock, output only on clock edges
Diffstat (limited to 'frontends/rtlil/rtlil_lexer.l')
0 files changed, 0 insertions, 0 deletions