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| author | whitequark <whitequark@whitequark.org> | 2020-12-23 23:15:56 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-23 23:15:56 +0000 |
| commit | deff6a9546699da5fc37e2fba622862daa120fd8 (patch) | |
| tree | 0c8eb479613490bf66ac1efa1b765045c494837a /frontends/ast | |
| parent | 8ef6b77dc366563410c88ec3687f777e74685377 (diff) | |
| parent | 999eec561752706a8ccb085a692684c745415985 (diff) | |
| download | yosys-deff6a9546699da5fc37e2fba622862daa120fd8.tar.gz yosys-deff6a9546699da5fc37e2fba622862daa120fd8.tar.bz2 yosys-deff6a9546699da5fc37e2fba622862daa120fd8.zip | |
Merge pull request #2501 from zachjs/genrtlil-tern-sign
genrtlil: fix mux2rtlil generated wire signedness
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 500ccf8c0..b8bfdf65e 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -141,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); + wire->is_signed = that->is_signed; for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) |