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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-19 18:38:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-19 18:38:25 +0200 |
| commit | f6629b9c29838879cec6a94d6cb47afc6fbd2db4 (patch) | |
| tree | a75ca899efb7a6d8889fada7a35e298521174457 /frontends/ast/simplify.cc | |
| parent | 9b8e06bee177f53c34a9dd6dd907a822f21659be (diff) | |
| download | yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.tar.gz yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.tar.bz2 yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.zip | |
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
Diffstat (limited to 'frontends/ast/simplify.cc')
| -rw-r--r-- | frontends/ast/simplify.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 79dc3b7c8..6ff117a44 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1490,6 +1490,11 @@ skip_dynamic_range_lvalue_expansion:; int mem_width, mem_size, addr_bits; children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits); + int addr_width_hint = -1; + bool addr_sign_hint = true; + children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint); + addr_bits = std::max(addr_bits, addr_width_hint); + AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); wire_addr->str = id_addr; current_ast_mod->children.push_back(wire_addr); |