From aee439360bba642dcbffe5b803aa9a994b11d183 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Mon, 18 May 2020 18:15:03 +0200 Subject: Add force_downto and force_upto wire attributes. Fixes #2058. --- frontends/ast/genrtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/ast/genrtlil.cc') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d4e9baa5f..cdc3adc9c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1055,7 +1055,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!range_valid) log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str()); - if (!(range_left >= range_right || (range_left == -1 && range_right == 0))) + if (!(range_left + 1 >= range_right)) log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); -- cgit v1.2.3