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| author | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
|---|---|---|
| committer | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
| commit | 9edf8869c18951ec2b75f074065f073da3253244 (patch) | |
| tree | 09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /frontends/ast/ast.h | |
| parent | 820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff) | |
| parent | 5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff) | |
| download | yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.gz yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.bz2 yosys-9edf8869c18951ec2b75f074065f073da3253244.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index e27ab10c2..3dd40238f 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -312,10 +312,10 @@ namespace AST AstNode *ast; bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire; ~AstModule() YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE; - std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet = false); - void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) YS_OVERRIDE; + std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet = false); + void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) YS_OVERRIDE; RTLIL::Module *clone() const YS_OVERRIDE; void loadconfig() const; }; |