Completed ngspice digital example with verilog tb

5 files changed, 76 insertions, 9 deletions

diff --git a/examples/cmos/README b/examples/cmos/README
new file mode 100644
index 000000000..a7b777595
--- /dev/null
+++ b/examples/cmos/README
@@ -0,0 +1,12 @@
+
+In this directory you will find out, how to generate a spice output
+operating in two modes, analog or event-driven mode supported by ngspice
+xspice sub-module.
+
+Each test bench can be run separately by either running:
+
+- testbench.sh, to start analog simulation or
+- testbench_digital.sh for mixed-signal digital simulation.
+
+The later case also includes pure verilog simulation using the iverilog
+and gtkwave to represent the results.
diff --git a/examples/cmos/counter_digital.ys b/examples/cmos/counter_digital.ys
new file mode 100644
index 000000000..a5e728e02
--- /dev/null
+++ b/examples/cmos/counter_digital.ys
@@ -0,0 +1,16 @@
+
+read_verilog counter.v
+read_verilog -lib cmos_cells.v
+
+proc;; memory;; techmap;;
+
+dfflibmap -liberty cmos_cells.lib
+abc -liberty cmos_cells.lib;;
+
+# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
+# dfflibmap -liberty osu025_stdcells.lib
+# abc -liberty osu025_stdcells.lib;;
+
+write_verilog synth.v
+write_spice -neg 0s -pos 1s synth.sp
+
diff --git a/examples/cmos/counter_tb.v b/examples/cmos/counter_tb.v
new file mode 100644
index 000000000..bcd7d992c
--- /dev/null
+++ b/examples/cmos/counter_tb.v
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+module counter_tb;
+
+  /* Make a reset pulse and specify dump file */
+  reg reset = 0;
+  initial begin
+     $dumpfile("counter_tb.vcd");
+     $dumpvars(0,counter_tb);
+
+     # 0 reset = 1;
+     # 4 reset = 0;
+     # 36 reset = 1;
+     # 4  reset = 0;
+     # 6 $finish;
+  end
+  
+  /* Make enable with period of 8 and 6,7 low */
+  reg en = 1;
+  always begin
+    en = 1;
+    #6;
+    en = 0;
+    #2;
+  end
+
+  /* Make a regular pulsing clock. */
+  reg clk = 0;
+  always #1 clk = !clk;
+  
+  /* UUT */
+  wire [2:0] count;
+  counter c1 (clk, reset, en, count);
+
+endmodule
diff --git a/examples/cmos/testbench_digital.sh b/examples/cmos/testbench_digital.sh
new file mode 100644
index 000000000..5836c97a6
--- /dev/null
+++ b/examples/cmos/testbench_digital.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+# iverlog simulation
+echo "Doing Verilog simulation with iverilog"
+iverilog -o dsn counter.v counter_tb.v 
+./dsn -lxt2
+gtkwave counter_tb.vcd &
+
+# yosys synthesis
+set -ex
+
+../../yosys counter_digital.ys
+
+# requires ngspice with xspice support enabled:
+ngspice testbench_digital.sp
diff --git a/examples/cmos/testbench_digital.sp b/examples/cmos/testbench_digital.sp
index dbfb83f62..c5f9d5987 100644
--- a/examples/cmos/testbench_digital.sp
+++ b/examples/cmos/testbench_digital.sp
@@ -1,13 +1,4 @@
 
-* supply voltages
-.global Vss Vdd
-Vss Vss 0 DC 0
-Vdd Vdd 0 DC 3
-
-* simple transistor model
-.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
-.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
-
 * load design and library
 .include cmos_cells_digital.sp
 .include synth.sp