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| author | Clifford Wolf <clifford@clifford.at> | 2016-03-02 12:07:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-03-02 12:07:57 +0100 |
| commit | b0ac32bc03b340b26e0d3bb778af1c915722abdf (patch) | |
| tree | 105f1df32d42a1d9bbd55b1b87719794d0c3d7a3 /examples | |
| parent | 5547fae4cf2e254d2f35f76f5c0b07abec2376dd (diff) | |
| download | yosys-b0ac32bc03b340b26e0d3bb778af1c915722abdf.tar.gz yosys-b0ac32bc03b340b26e0d3bb778af1c915722abdf.tar.bz2 yosys-b0ac32bc03b340b26e0d3bb778af1c915722abdf.zip | |
Added digital (xspice) example code to examples/cmos/
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/cmos/cmos_cells_digital.sp | 31 | ||||
| -rw-r--r-- | examples/cmos/testbench.sh | 3 | ||||
| -rw-r--r-- | examples/cmos/testbench.sp | 2 | ||||
| -rw-r--r-- | examples/cmos/testbench_digital.sp | 35 |
4 files changed, 70 insertions, 1 deletions
diff --git a/examples/cmos/cmos_cells_digital.sp b/examples/cmos/cmos_cells_digital.sp new file mode 100644 index 000000000..e1cb82a2f --- /dev/null +++ b/examples/cmos/cmos_cells_digital.sp @@ -0,0 +1,31 @@ + +.SUBCKT BUF A Y +.model buffer1 d_buffer +Abuf A Y buffer1 +.ENDS NOT + +.SUBCKT NOT A Y +.model not1 d_inverter +Anot A Y not1 +.ENDS NOT + +.SUBCKT NAND A B Y +.model nand1 d_nand +Anand [A B] Y nand1 +.ENDS NAND + +.SUBCKT NOR A B Y +.model nor1 d_nor +Anand [A B] Y nor1 +.ENDS NOR + +.SUBCKT DLATCH E D Q +.model latch1 d_latch +Alatch D E null null Q nQ latch1 +.ENDS DLATCH + +.SUBCKT DFF C D Q +.model dff1 d_dff +Adff D C null null Q nQ dff1 +.ENDS DFF + diff --git a/examples/cmos/testbench.sh b/examples/cmos/testbench.sh index 061704b64..e2a203ff5 100644 --- a/examples/cmos/testbench.sh +++ b/examples/cmos/testbench.sh @@ -5,3 +5,6 @@ set -ex ../../yosys counter.ys ngspice testbench.sp +# requires ngspice with xspice support enabled: +#ngspice testbench_digital.sp + diff --git a/examples/cmos/testbench.sp b/examples/cmos/testbench.sp index 95d2f67cd..e571d2815 100644 --- a/examples/cmos/testbench.sp +++ b/examples/cmos/testbench.sp @@ -9,8 +9,8 @@ Vdd Vdd 0 DC 3 .MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 * load design and library -.include synth.sp .include cmos_cells.sp +.include synth.sp * input signals Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) diff --git a/examples/cmos/testbench_digital.sp b/examples/cmos/testbench_digital.sp new file mode 100644 index 000000000..dbfb83f62 --- /dev/null +++ b/examples/cmos/testbench_digital.sp @@ -0,0 +1,35 @@ + +* supply voltages +.global Vss Vdd +Vss Vss 0 DC 0 +Vdd Vdd 0 DC 3 + +* simple transistor model +.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 +.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 + +* load design and library +.include cmos_cells_digital.sp +.include synth.sp + +* input signals +Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) +Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40) +Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8) + +Xuut dclk drst den dout0 dout1 dout2 counter +* Bridge to digital +.model adc_buff adc_bridge(in_low = 0.8 in_high=2) +.model dac_buff dac_bridge(out_high = 3.5) +Aad [clk rst en] [dclk drst den] adc_buff +Ada [dout0 dout1 dout2] [out0 out1 out2] dac_buff + + +.tran 0.01 50 + +.control +run +plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30 +.endc + +.end |