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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-04-08 20:54:31 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-04-12 15:11:09 +0200 |
| commit | 2021ddecb39d3848e180cd7e078facf82132440f (patch) | |
| tree | a768dd33906dae73482f79cd78c8bce8ddd56f0d /examples/intel/MAX10/top.v | |
| parent | 41d4e91f388f41c97f71567cd5a0f5652a5968fd (diff) | |
| download | yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.gz yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.bz2 yosys-2021ddecb39d3848e180cd7e078facf82132440f.zip | |
Squelch trailing whitespace
Diffstat (limited to 'examples/intel/MAX10/top.v')
| -rw-r--r-- | examples/intel/MAX10/top.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/intel/MAX10/top.v b/examples/intel/MAX10/top.v index 75c778feb..2bada0e21 100644 --- a/examples/intel/MAX10/top.v +++ b/examples/intel/MAX10/top.v @@ -1,8 +1,8 @@ `default_nettype none module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, input wire [15:0] SW ); - - + + sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7)); sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1)); sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0)); @@ -11,5 +11,5 @@ module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4])); sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8])); sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12])); - + endmodule |