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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-04-08 20:54:31 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-04-12 15:11:09 +0200 |
| commit | 2021ddecb39d3848e180cd7e078facf82132440f (patch) | |
| tree | a768dd33906dae73482f79cd78c8bce8ddd56f0d /examples | |
| parent | 41d4e91f388f41c97f71567cd5a0f5652a5968fd (diff) | |
| download | yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.gz yosys-2021ddecb39d3848e180cd7e078facf82132440f.tar.bz2 yosys-2021ddecb39d3848e180cd7e078facf82132440f.zip | |
Squelch trailing whitespace
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/cmos/counter_tb.v | 4 | ||||
| -rw-r--r-- | examples/cmos/testbench_digital.sh | 2 | ||||
| -rw-r--r-- | examples/intel/DE2i-150/sevenseg.v | 22 | ||||
| -rw-r--r-- | examples/intel/DE2i-150/top.v | 6 | ||||
| -rw-r--r-- | examples/intel/MAX10/sevenseg.v | 22 | ||||
| -rw-r--r-- | examples/intel/MAX10/top.v | 6 |
6 files changed, 31 insertions, 31 deletions
diff --git a/examples/cmos/counter_tb.v b/examples/cmos/counter_tb.v index bcd7d992c..11e82507e 100644 --- a/examples/cmos/counter_tb.v +++ b/examples/cmos/counter_tb.v @@ -12,7 +12,7 @@ module counter_tb; # 4 reset = 0; # 6 $finish; end - + /* Make enable with period of 8 and 6,7 low */ reg en = 1; always begin @@ -25,7 +25,7 @@ module counter_tb; /* Make a regular pulsing clock. */ reg clk = 0; always #1 clk = !clk; - + /* UUT */ wire [2:0] count; counter c1 (clk, reset, en, count); diff --git a/examples/cmos/testbench_digital.sh b/examples/cmos/testbench_digital.sh index afaaf4d43..d7ab0fe1f 100644 --- a/examples/cmos/testbench_digital.sh +++ b/examples/cmos/testbench_digital.sh @@ -4,7 +4,7 @@ set -ex # iverlog simulation echo "Doing Verilog simulation with iverilog" -iverilog -o counter_tb counter.v counter_tb.v +iverilog -o counter_tb counter.v counter_tb.v ./counter_tb; gtkwave counter_tb.gtkw & # yosys synthesis diff --git a/examples/intel/DE2i-150/sevenseg.v b/examples/intel/DE2i-150/sevenseg.v index b845f5211..06cf7c146 100644 --- a/examples/intel/DE2i-150/sevenseg.v +++ b/examples/intel/DE2i-150/sevenseg.v @@ -3,15 +3,15 @@ module sevenseg ( output reg [6:0] HEX0, always @(*) begin case(SW) - 4'h1: HEX0 = 7'b1111001; - 4'h2: HEX0 = 7'b0100100; - 4'h3: HEX0 = 7'b0110000; - 4'h4: HEX0 = 7'b0011001; - 4'h5: HEX0 = 7'b0010010; - 4'h6: HEX0 = 7'b0000010; - 4'h7: HEX0 = 7'b1111000; - 4'h8: HEX0 = 7'b0000000; - 4'h9: HEX0 = 7'b0011000; + 4'h1: HEX0 = 7'b1111001; + 4'h2: HEX0 = 7'b0100100; + 4'h3: HEX0 = 7'b0110000; + 4'h4: HEX0 = 7'b0011001; + 4'h5: HEX0 = 7'b0010010; + 4'h6: HEX0 = 7'b0000010; + 4'h7: HEX0 = 7'b1111000; + 4'h8: HEX0 = 7'b0000000; + 4'h9: HEX0 = 7'b0011000; 4'ha: HEX0 = 7'b0001000; 4'hb: HEX0 = 7'b0000011; 4'hc: HEX0 = 7'b1000110; @@ -20,6 +20,6 @@ module sevenseg ( output reg [6:0] HEX0, 4'hf: HEX0 = 7'b0001110; 4'h0: HEX0 = 7'b1000000; endcase // case (SW) - end - + end + endmodule diff --git a/examples/intel/DE2i-150/top.v b/examples/intel/DE2i-150/top.v index 75c778feb..2bada0e21 100644 --- a/examples/intel/DE2i-150/top.v +++ b/examples/intel/DE2i-150/top.v @@ -1,8 +1,8 @@ `default_nettype none module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, input wire [15:0] SW ); - - + + sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7)); sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1)); sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0)); @@ -11,5 +11,5 @@ module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4])); sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8])); sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12])); - + endmodule diff --git a/examples/intel/MAX10/sevenseg.v b/examples/intel/MAX10/sevenseg.v index b845f5211..06cf7c146 100644 --- a/examples/intel/MAX10/sevenseg.v +++ b/examples/intel/MAX10/sevenseg.v @@ -3,15 +3,15 @@ module sevenseg ( output reg [6:0] HEX0, always @(*) begin case(SW) - 4'h1: HEX0 = 7'b1111001; - 4'h2: HEX0 = 7'b0100100; - 4'h3: HEX0 = 7'b0110000; - 4'h4: HEX0 = 7'b0011001; - 4'h5: HEX0 = 7'b0010010; - 4'h6: HEX0 = 7'b0000010; - 4'h7: HEX0 = 7'b1111000; - 4'h8: HEX0 = 7'b0000000; - 4'h9: HEX0 = 7'b0011000; + 4'h1: HEX0 = 7'b1111001; + 4'h2: HEX0 = 7'b0100100; + 4'h3: HEX0 = 7'b0110000; + 4'h4: HEX0 = 7'b0011001; + 4'h5: HEX0 = 7'b0010010; + 4'h6: HEX0 = 7'b0000010; + 4'h7: HEX0 = 7'b1111000; + 4'h8: HEX0 = 7'b0000000; + 4'h9: HEX0 = 7'b0011000; 4'ha: HEX0 = 7'b0001000; 4'hb: HEX0 = 7'b0000011; 4'hc: HEX0 = 7'b1000110; @@ -20,6 +20,6 @@ module sevenseg ( output reg [6:0] HEX0, 4'hf: HEX0 = 7'b0001110; 4'h0: HEX0 = 7'b1000000; endcase // case (SW) - end - + end + endmodule diff --git a/examples/intel/MAX10/top.v b/examples/intel/MAX10/top.v index 75c778feb..2bada0e21 100644 --- a/examples/intel/MAX10/top.v +++ b/examples/intel/MAX10/top.v @@ -1,8 +1,8 @@ `default_nettype none module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, input wire [15:0] SW ); - - + + sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7)); sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1)); sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0)); @@ -11,5 +11,5 @@ module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4])); sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8])); sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12])); - + endmodule |