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| author | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
|---|---|---|
| committer | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
| commit | b34385ec924b6067c1f82bdbae923f8062518956 (patch) | |
| tree | 3d09d194e53fa575628b890df7cc106efdcd4742 /examples/cmos/testbench_digital.sp | |
| parent | b0ac32bc03b340b26e0d3bb778af1c915722abdf (diff) | |
| download | yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.gz yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.bz2 yosys-b34385ec924b6067c1f82bdbae923f8062518956.zip | |
Completed ngspice digital example with verilog tb
Diffstat (limited to 'examples/cmos/testbench_digital.sp')
| -rw-r--r-- | examples/cmos/testbench_digital.sp | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/examples/cmos/testbench_digital.sp b/examples/cmos/testbench_digital.sp index dbfb83f62..c5f9d5987 100644 --- a/examples/cmos/testbench_digital.sp +++ b/examples/cmos/testbench_digital.sp @@ -1,13 +1,4 @@ -* supply voltages -.global Vss Vdd -Vss Vss 0 DC 0 -Vdd Vdd 0 DC 3 - -* simple transistor model -.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 -.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 - * load design and library .include cmos_cells_digital.sp .include synth.sp |