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author | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
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committer | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
commit | b34385ec924b6067c1f82bdbae923f8062518956 (patch) | |
tree | 3d09d194e53fa575628b890df7cc106efdcd4742 /examples/cmos/testbench_digital.sh | |
parent | b0ac32bc03b340b26e0d3bb778af1c915722abdf (diff) | |
download | yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.gz yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.bz2 yosys-b34385ec924b6067c1f82bdbae923f8062518956.zip |
Completed ngspice digital example with verilog tb
Diffstat (limited to 'examples/cmos/testbench_digital.sh')
-rw-r--r-- | examples/cmos/testbench_digital.sh | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/examples/cmos/testbench_digital.sh b/examples/cmos/testbench_digital.sh new file mode 100644 index 000000000..5836c97a6 --- /dev/null +++ b/examples/cmos/testbench_digital.sh @@ -0,0 +1,15 @@ +#!/bin/bash + +# iverlog simulation +echo "Doing Verilog simulation with iverilog" +iverilog -o dsn counter.v counter_tb.v +./dsn -lxt2 +gtkwave counter_tb.vcd & + +# yosys synthesis +set -ex + +../../yosys counter_digital.ys + +# requires ngspice with xspice support enabled: +ngspice testbench_digital.sp |