Completed ngspice digital example with verilog tb

1 files changed, 15 insertions, 0 deletions

diff --git a/examples/cmos/testbench_digital.sh b/examples/cmos/testbench_digital.sh
new file mode 100644
index 000000000..5836c97a6
--- /dev/null
+++ b/examples/cmos/testbench_digital.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+# iverlog simulation
+echo "Doing Verilog simulation with iverilog"
+iverilog -o dsn counter.v counter_tb.v 
+./dsn -lxt2
+gtkwave counter_tb.vcd &
+
+# yosys synthesis
+set -ex
+
+../../yosys counter_digital.ys
+
+# requires ngspice with xspice support enabled:
+ngspice testbench_digital.sp