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| author | Clifford Wolf <clifford@clifford.at> | 2016-03-02 12:07:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-03-02 12:07:57 +0100 |
| commit | b0ac32bc03b340b26e0d3bb778af1c915722abdf (patch) | |
| tree | 105f1df32d42a1d9bbd55b1b87719794d0c3d7a3 /examples/cmos/testbench.sp | |
| parent | 5547fae4cf2e254d2f35f76f5c0b07abec2376dd (diff) | |
| download | yosys-b0ac32bc03b340b26e0d3bb778af1c915722abdf.tar.gz yosys-b0ac32bc03b340b26e0d3bb778af1c915722abdf.tar.bz2 yosys-b0ac32bc03b340b26e0d3bb778af1c915722abdf.zip | |
Added digital (xspice) example code to examples/cmos/
Diffstat (limited to 'examples/cmos/testbench.sp')
| -rw-r--r-- | examples/cmos/testbench.sp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/cmos/testbench.sp b/examples/cmos/testbench.sp index 95d2f67cd..e571d2815 100644 --- a/examples/cmos/testbench.sp +++ b/examples/cmos/testbench.sp @@ -9,8 +9,8 @@ Vdd Vdd 0 DC 3 .MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 * load design and library -.include synth.sp .include cmos_cells.sp +.include synth.sp * input signals Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) |