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| author | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
|---|---|---|
| committer | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
| commit | b34385ec924b6067c1f82bdbae923f8062518956 (patch) | |
| tree | 3d09d194e53fa575628b890df7cc106efdcd4742 /examples/cmos/counter_digital.ys | |
| parent | b0ac32bc03b340b26e0d3bb778af1c915722abdf (diff) | |
| download | yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.gz yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.bz2 yosys-b34385ec924b6067c1f82bdbae923f8062518956.zip | |
Completed ngspice digital example with verilog tb
Diffstat (limited to 'examples/cmos/counter_digital.ys')
| -rw-r--r-- | examples/cmos/counter_digital.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/examples/cmos/counter_digital.ys b/examples/cmos/counter_digital.ys new file mode 100644 index 000000000..a5e728e02 --- /dev/null +++ b/examples/cmos/counter_digital.ys @@ -0,0 +1,16 @@ + +read_verilog counter.v +read_verilog -lib cmos_cells.v + +proc;; memory;; techmap;; + +dfflibmap -liberty cmos_cells.lib +abc -liberty cmos_cells.lib;; + +# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib +# dfflibmap -liberty osu025_stdcells.lib +# abc -liberty osu025_stdcells.lib;; + +write_verilog synth.v +write_spice -neg 0s -pos 1s synth.sp + |