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| author | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
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| committer | Uros Platise <uros@isotel.eu> | 2016-03-05 08:34:05 +0100 |
| commit | b34385ec924b6067c1f82bdbae923f8062518956 (patch) | |
| tree | 3d09d194e53fa575628b890df7cc106efdcd4742 /examples/cmos/README | |
| parent | b0ac32bc03b340b26e0d3bb778af1c915722abdf (diff) | |
| download | yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.gz yosys-b34385ec924b6067c1f82bdbae923f8062518956.tar.bz2 yosys-b34385ec924b6067c1f82bdbae923f8062518956.zip | |
Completed ngspice digital example with verilog tb
Diffstat (limited to 'examples/cmos/README')
| -rw-r--r-- | examples/cmos/README | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/examples/cmos/README b/examples/cmos/README new file mode 100644 index 000000000..a7b777595 --- /dev/null +++ b/examples/cmos/README @@ -0,0 +1,12 @@ + +In this directory you will find out, how to generate a spice output +operating in two modes, analog or event-driven mode supported by ngspice +xspice sub-module. + +Each test bench can be run separately by either running: + +- testbench.sh, to start analog simulation or +- testbench_digital.sh for mixed-signal digital simulation. + +The later case also includes pure verilog simulation using the iverilog +and gtkwave to represent the results. |