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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-05 15:20:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 15:20:03 -0800 |
| commit | ba0da6371e6bffc3e79a0d5388a508e2b7ea775b (patch) | |
| tree | ba9b5e1f25d3e7dd51cfc7458ff88d4640fbb365 /examples/anlogic/demo.v | |
| parent | 855b9dc60661f79252d1f49e0a93911ce7b5a9b4 (diff) | |
| parent | 32a901ddf21711e2b2fe2a0a8719ff7f69fd9489 (diff) | |
| download | yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.tar.gz yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.tar.bz2 yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.zip | |
Merge pull request #851 from kprasadvnsi/master
Added examples/anlogic/
Diffstat (limited to 'examples/anlogic/demo.v')
| -rw-r--r-- | examples/anlogic/demo.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v new file mode 100644 index 000000000..a7edf4e37 --- /dev/null +++ b/examples/anlogic/demo.v @@ -0,0 +1,18 @@ +module demo ( + input wire CLK_IN, + output wire R_LED +); + parameter time1 = 30'd12_000_000; + reg led_state; + reg [29:0] count; + + always @(posedge CLK_IN)begin + if(count == time1)begin + count<= 30'd0; + led_state <= ~led_state; + end + else + count <= count + 1'b1; + end + assign R_LED = led_state; +endmodule
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