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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-05 15:20:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 15:20:03 -0800 |
| commit | ba0da6371e6bffc3e79a0d5388a508e2b7ea775b (patch) | |
| tree | ba9b5e1f25d3e7dd51cfc7458ff88d4640fbb365 /examples | |
| parent | 855b9dc60661f79252d1f49e0a93911ce7b5a9b4 (diff) | |
| parent | 32a901ddf21711e2b2fe2a0a8719ff7f69fd9489 (diff) | |
| download | yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.tar.gz yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.tar.bz2 yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.zip | |
Merge pull request #851 from kprasadvnsi/master
Added examples/anlogic/
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/anlogic/.gitignore | 4 | ||||
| -rw-r--r-- | examples/anlogic/README | 13 | ||||
| -rwxr-xr-x | examples/anlogic/build.sh | 4 | ||||
| -rw-r--r-- | examples/anlogic/build.tcl | 11 | ||||
| -rw-r--r-- | examples/anlogic/demo.adc | 2 | ||||
| -rw-r--r-- | examples/anlogic/demo.v | 18 | ||||
| -rw-r--r-- | examples/anlogic/demo.ys | 3 |
7 files changed, 55 insertions, 0 deletions
diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore new file mode 100644 index 000000000..fa9424cd8 --- /dev/null +++ b/examples/anlogic/.gitignore @@ -0,0 +1,4 @@ +demo.bit +demo_phy.area +full.v +*.log
\ No newline at end of file diff --git a/examples/anlogic/README b/examples/anlogic/README new file mode 100644 index 000000000..99143cce0 --- /dev/null +++ b/examples/anlogic/README @@ -0,0 +1,13 @@ +LED Blink project for Anlogic Lichee Tang board. + +Follow the install instructions for the Tang Dynasty IDE from given link below. + +https://tang.sipeed.com/en/getting-started/installing-td-ide/linux/ + + +set TD_HOME env variable to the full path to the TD <TD Install Directory> as follow. + +export TD_HOME=<TD Install Directory> + +then run "bash build.sh" in this directory. + diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh new file mode 100755 index 000000000..8b77a32d6 --- /dev/null +++ b/examples/anlogic/build.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -ex +yosys demo.ys +$TD_HOME/bin/td build.tcl
\ No newline at end of file diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl new file mode 100644 index 000000000..db8c3b347 --- /dev/null +++ b/examples/anlogic/build.tcl @@ -0,0 +1,11 @@ +import_device eagle_s20.db -package BG256 +read_verilog full.v -top demo +read_adc demo.adc +optimize_rtl +map_macro +map +pack +place +route +report_area -io_info -file demo_phy.area +bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000 diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc new file mode 100644 index 000000000..c8fbaed3e --- /dev/null +++ b/examples/anlogic/demo.adc @@ -0,0 +1,2 @@ +set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ +set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED
\ No newline at end of file diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v new file mode 100644 index 000000000..a7edf4e37 --- /dev/null +++ b/examples/anlogic/demo.v @@ -0,0 +1,18 @@ +module demo ( + input wire CLK_IN, + output wire R_LED +); + parameter time1 = 30'd12_000_000; + reg led_state; + reg [29:0] count; + + always @(posedge CLK_IN)begin + if(count == time1)begin + count<= 30'd0; + led_state <= ~led_state; + end + else + count <= count + 1'b1; + end + assign R_LED = led_state; +endmodule
\ No newline at end of file diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys new file mode 100644 index 000000000..5687bcd31 --- /dev/null +++ b/examples/anlogic/demo.ys @@ -0,0 +1,3 @@ +read_verilog demo.v +synth_anlogic -top demo +write_verilog full.v
\ No newline at end of file |