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author | Eddie Hung <eddie@fpgeh.com> | 2020-03-02 12:32:27 -0800 |
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committer | GitHub <noreply@github.com> | 2020-03-02 12:32:27 -0800 |
commit | 4f889b2f57b732083dd4bf336a0d361f70e5b2d0 (patch) | |
tree | 5f8e46c0273e9e9bee1d6e6a6775b3f58ec302da /backends | |
parent | b1e248b0e6c7945870c83ac82bfb4ed8e9d8ff66 (diff) | |
parent | 090e54569a58b26d616806337c28507d199ca43c (diff) | |
download | yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.gz yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.bz2 yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.zip |
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 72 |
1 files changed, 34 insertions, 38 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3cf36aca8..402f41597 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -47,6 +47,7 @@ inline static uint32_t bswap32(uint32_t x) #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/utils.h" +#include "kernel/timinginfo.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -184,9 +185,9 @@ struct XAigerWriter } } - dict<IdString,dict<IdString,std::vector<int>>> arrivals_cache; + TimingInfo timing; + for (auto cell : module->cells()) { - RTLIL::Module* inst_module = module->design->module(cell->type); if (!cell->has_keep_attr()) { if (cell->type == "$_NOT_") { @@ -227,8 +228,18 @@ struct XAigerWriter continue; } - if (inst_module) { - bool abc9_flop = false; + if (cell->type.in("$specify2", "$specify3", "$specrule")) + continue; + } + + RTLIL::Module* inst_module = module->design->module(cell->type); + if (inst_module) { + IdString derived_type = inst_module->derive(module->design, cell->parameters); + inst_module = module->design->module(derived_type); + log_assert(inst_module); + + bool abc9_flop = false; + if (!cell->has_keep_attr()) { auto it = cell->attributes.find("\\abc9_box_seq"); if (it != cell->attributes.end()) { int abc9_box_seq = it->second.as_int(); @@ -241,50 +252,34 @@ struct XAigerWriter if (!abc9_flop) continue; } + } - auto &cell_arrivals = arrivals_cache[cell->type]; - for (const auto &conn : cell->connections()) { - auto port_wire = inst_module->wire(conn.first); - if (!port_wire->port_output) - continue; - - auto r = cell_arrivals.insert(conn.first); - auto &arrivals = r.first->second; - if (r.second) { - auto it = port_wire->attributes.find("\\abc9_arrival"); - if (it == port_wire->attributes.end()) - continue; - if (it->second.flags == 0) - arrivals.emplace_back(it->second.as_int()); - else - for (const auto &tok : split_tokens(it->second.decode_string())) - arrivals.push_back(atoi(tok.c_str())); - } + if (!timing.count(derived_type)) + timing.setup_module(inst_module); + auto &t = timing.at(derived_type).arrival; + for (const auto &conn : cell->connections()) { + auto port_wire = inst_module->wire(conn.first); + if (!port_wire->port_output) + continue; - if (arrivals.empty()) + for (int i = 0; i < GetSize(conn.second); i++) { + auto d = t.at(TimingInfo::NameBit(conn.first,i), 0); + if (d == 0) continue; - if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) - log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), - GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); - - auto jt = arrivals.begin(); #ifndef NDEBUG if (ys_debug(1)) { - static std::set<std::pair<IdString,IdString>> seen; - if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); + static std::set<std::tuple<IdString,IdString,int>> seen; + if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n", + log_id(cell->type), log_id(conn.first), i, d); } #endif - for (auto bit : sigmap(conn.second)) { - arrival_times[bit] = *jt; - if (arrivals.size() > 1) - jt++; - } + arrival_times[conn.second[i]] = d; } - - if (abc9_flop) - continue; } + + if (abc9_flop) + continue; } bool cell_known = inst_module || cell->known(); @@ -661,6 +656,7 @@ struct XAigerWriter write_s_buffer(0); } + // Use arrival time from output of flop box write_i_buffer(arrival_times.at(d, 0)); //write_o_buffer(0); } |