From 12d70ca8fbad73f2615e711e786f8b90fa005bee Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Feb 2020 15:25:30 -0800 Subject: xilinx: improve specify functionality --- backends/aiger/xaiger.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3cf36aca8..c996b0776 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -227,6 +227,9 @@ struct XAigerWriter continue; } + if (cell->type.in("$specify2", "$specify3", "$specrule")) + continue; + if (inst_module) { bool abc9_flop = false; auto it = cell->attributes.find("\\abc9_box_seq"); -- cgit v1.2.3 From e22fee6cdd905535c50c9b6d96a89e994944ea2c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 11:15:59 -0800 Subject: abc9_ops: ignore (* abc9_flop *) if not '-dff' --- backends/aiger/xaiger.cc | 82 ++++++++++++++++++++++++++---------------------- 1 file changed, 44 insertions(+), 38 deletions(-) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index c996b0776..16d48a932 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -186,7 +186,6 @@ struct XAigerWriter dict>> arrivals_cache; for (auto cell : module->cells()) { - RTLIL::Module* inst_module = module->design->module(cell->type); if (!cell->has_keep_attr()) { if (cell->type == "$_NOT_") { @@ -229,9 +228,16 @@ struct XAigerWriter if (cell->type.in("$specify2", "$specify3", "$specrule")) continue; + } - if (inst_module) { - bool abc9_flop = false; + RTLIL::Module* inst_module = module->design->module(cell->type); + if (inst_module) { + IdString derived_type = inst_module->derive(module->design, cell->parameters); + inst_module = module->design->module(derived_type); + log_assert(inst_module); + + bool abc9_flop = false; + if (!cell->has_keep_attr()) { auto it = cell->attributes.find("\\abc9_box_seq"); if (it != cell->attributes.end()) { int abc9_box_seq = it->second.as_int(); @@ -244,50 +250,50 @@ struct XAigerWriter if (!abc9_flop) continue; } + } - auto &cell_arrivals = arrivals_cache[cell->type]; - for (const auto &conn : cell->connections()) { - auto port_wire = inst_module->wire(conn.first); - if (!port_wire->port_output) - continue; - - auto r = cell_arrivals.insert(conn.first); - auto &arrivals = r.first->second; - if (r.second) { - auto it = port_wire->attributes.find("\\abc9_arrival"); - if (it == port_wire->attributes.end()) - continue; - if (it->second.flags == 0) - arrivals.emplace_back(it->second.as_int()); - else - for (const auto &tok : split_tokens(it->second.decode_string())) - arrivals.push_back(atoi(tok.c_str())); - } + auto &cell_arrivals = arrivals_cache[derived_type]; + for (const auto &conn : cell->connections()) { + auto port_wire = inst_module->wire(conn.first); + if (!port_wire->port_output) + continue; - if (arrivals.empty()) + auto r = cell_arrivals.insert(conn.first); + auto &arrivals = r.first->second; + if (r.second) { + auto it = port_wire->attributes.find("\\abc9_arrival"); + if (it == port_wire->attributes.end()) continue; + if (it->second.flags == 0) + arrivals.emplace_back(it->second.as_int()); + else { + for (const auto &tok : split_tokens(it->second.decode_string())) + arrivals.push_back(atoi(tok.c_str())); + if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) + log_error("%s.%s is %d bits wide but abc9_arrival = '%s' has %d value(s)!\n", log_id(cell->type), log_id(conn.first), + GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); + } + } - if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) - log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), - GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); + if (arrivals.empty()) + continue; - auto jt = arrivals.begin(); + auto jt = arrivals.begin(); #ifndef NDEBUG - if (ys_debug(1)) { - static std::set> seen; - if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); - } + if (ys_debug(1)) { + static std::set> seen; + if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); + } #endif - for (auto bit : sigmap(conn.second)) { - arrival_times[bit] = *jt; - if (arrivals.size() > 1) - jt++; - } + for (auto bit : sigmap(conn.second)) { + arrival_times[bit] = *jt; + if (arrivals.size() > 1) + jt++; } - - if (abc9_flop) - continue; } + + if (abc9_flop) + continue; } bool cell_known = inst_module || cell->known(); -- cgit v1.2.3 From 1ef1ca812bd057fe0404893e357c10361225e393 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 14 Feb 2020 12:54:47 -0800 Subject: Get rid of (* abc9_{arrival,required} *) entirely --- backends/aiger/xaiger.cc | 44 +++++++++++++++----------------------------- 1 file changed, 15 insertions(+), 29 deletions(-) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 16d48a932..2a39d225d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -47,6 +47,7 @@ inline static uint32_t bswap32(uint32_t x) #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/utils.h" +#include "kernel/timinginfo.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -184,7 +185,8 @@ struct XAigerWriter } } - dict>> arrivals_cache; + TimingInfo timing; + for (auto cell : module->cells()) { if (!cell->has_keep_attr()) { if (cell->type == "$_NOT_") @@ -252,43 +254,27 @@ struct XAigerWriter } } - auto &cell_arrivals = arrivals_cache[derived_type]; + if (!timing.count(derived_type)) + timing.setup_module(inst_module); + auto &t = timing.at(derived_type).arrival; for (const auto &conn : cell->connections()) { auto port_wire = inst_module->wire(conn.first); if (!port_wire->port_output) continue; - auto r = cell_arrivals.insert(conn.first); - auto &arrivals = r.first->second; - if (r.second) { - auto it = port_wire->attributes.find("\\abc9_arrival"); - if (it == port_wire->attributes.end()) + for (int i = 0; i < GetSize(conn.second); i++) { + auto d = t.at(SigBit(port_wire,i), 0); + if (d == 0) continue; - if (it->second.flags == 0) - arrivals.emplace_back(it->second.as_int()); - else { - for (const auto &tok : split_tokens(it->second.decode_string())) - arrivals.push_back(atoi(tok.c_str())); - if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) - log_error("%s.%s is %d bits wide but abc9_arrival = '%s' has %d value(s)!\n", log_id(cell->type), log_id(conn.first), - GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); - } - } - if (arrivals.empty()) - continue; - - auto jt = arrivals.begin(); #ifndef NDEBUG - if (ys_debug(1)) { - static std::set> seen; - if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); - } + if (ys_debug(1)) { + static std::set> seen; + if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n", + log_id(cell->type), log_id(conn.first), i, d); + } #endif - for (auto bit : sigmap(conn.second)) { - arrival_times[bit] = *jt; - if (arrivals.size() > 1) - jt++; + arrival_times[conn.second[i]] = d; } } -- cgit v1.2.3 From 5ff60d2057992bdc9f0ff04eee78d7bf6be0ee44 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 14 Feb 2020 13:43:34 -0800 Subject: write_xaiger: add comment about arrival times of flop outputs --- backends/aiger/xaiger.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 2a39d225d..dc0f997fe 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -656,6 +656,7 @@ struct XAigerWriter write_s_buffer(0); } + // Use arrival time from output of flop box write_i_buffer(arrival_times.at(d, 0)); //write_o_buffer(0); } -- cgit v1.2.3 From 6bb3d9f9c09993960a5a91fa51f163a7e67e2503 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 18 Feb 2020 11:02:28 -0800 Subject: Make TimingInfo::TimingInfo(SigBit) constructor explicit --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends') diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index dc0f997fe..402f41597 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -263,7 +263,7 @@ struct XAigerWriter continue; for (int i = 0; i < GetSize(conn.second); i++) { - auto d = t.at(SigBit(port_wire,i), 0); + auto d = t.at(TimingInfo::NameBit(conn.first,i), 0); if (d == 0) continue; -- cgit v1.2.3