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authorEddie Hung <eddie@fpgeh.com>2019-06-14 13:08:38 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-14 13:08:38 -0700
commit0fa6a441f1a222b039975cf622ddca479a65cf24 (patch)
treed30dddf79518226fb7666b19ca894fec8a68efb5 /backends
parent2d85725604271c658382e8fdd8ff28275fb94b03 (diff)
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Check that whiteboxes are synthesisable
Diffstat (limited to 'backends')
-rw-r--r--backends/aiger/xaiger.cc12
1 files changed, 8 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3f7edc627..bc722e492 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -722,7 +722,7 @@ struct XAigerWriter
write_h_buffer(box_list.size());
RTLIL::Module *holes_module = nullptr;
- holes_module = module->design->addModule("\\__holes__");
+ holes_module = module->design->addModule("$__holes__");
log_assert(holes_module);
int port_id = 1;
@@ -822,17 +822,21 @@ struct XAigerWriter
Pass::call(holes_module->design, "flatten -wb");
- // TODO: Should techmap all lib_whitebox-es once
+ // TODO: Should techmap/AIG all lib_whitebox-es once
Pass::call(holes_module->design, "techmap");
Pass::call(holes_module->design, "aigmap");
- Pass::call(holes_module->design, "clean -purge");
+ for (auto cell : holes_module->cells())
+ if (!cell->type.in("$_NOT_", "$_AND_"))
+ log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
- holes_module->design->selection_stack.pop_back();
+ Pass::call(holes_module->design, "clean -purge");
std::stringstream a_buffer;
XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/);
+ holes_module->design->selection_stack.pop_back();
+
f << "a";
std::string buffer_str = a_buffer.str();
int32_t buffer_size_be = to_big_endian(buffer_str.size());