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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 13:07:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 13:07:56 -0700 |
| commit | 2d85725604271c658382e8fdd8ff28275fb94b03 (patch) | |
| tree | e20bd94404cc1d4992cd662207ffe7edd4c96690 /backends | |
| parent | 8fa74287a71fc3527cf48c7fb2c4a635ee832b72 (diff) | |
| download | yosys-2d85725604271c658382e8fdd8ff28275fb94b03.tar.gz yosys-2d85725604271c658382e8fdd8ff28275fb94b03.tar.bz2 yosys-2d85725604271c658382e8fdd8ff28275fb94b03.zip | |
Get rid of compiler warnings
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7cb311736..3f7edc627 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -190,7 +190,7 @@ struct XAigerWriter bool abc_box_seen = false; - for (auto cell : module->cells()) { + for (auto cell : module->selected_cells()) { if (cell->type == "$_NOT_") { SigBit A = sigmap(cell->getPort("\\A").as_bit()); @@ -312,7 +312,7 @@ struct XAigerWriter TopoSort<IdString, RTLIL::sort_by_id_str> toposort; dict<SigBit, pool<IdString>> bit_drivers, bit_users; - for (auto cell : module->cells()) { + for (auto cell : module->selected_cells()) { RTLIL::Module* inst_module = module->design->module(cell->type); if (!inst_module || !inst_module->attributes.count("\\abc_box_id")) continue; |