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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-03 12:41:46 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-03 12:41:46 +0100 |
| commit | fd2c224c04b0fff83d2255c86533686fe2dc8883 (patch) | |
| tree | eb3e19bd986c98753496ea1957edc64a0db3c37e /backends/verilog | |
| parent | a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84 (diff) | |
| download | yosys-fd2c224c04b0fff83d2255c86533686fe2dc8883.tar.gz yosys-fd2c224c04b0fff83d2255c86533686fe2dc8883.tar.bz2 yosys-fd2c224c04b0fff83d2255c86533686fe2dc8883.zip | |
memory_bram transp support
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions