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| author | whitequark <whitequark@whitequark.org> | 2020-06-17 06:06:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-17 06:06:58 +0000 |
| commit | eaf66037a59fc55d385d0bb4216b08fd565c05f1 (patch) | |
| tree | 6414adb94b9cd8ece7de6d9ce92ec1be2672d2e5 /backends/verilog | |
| parent | 39ba90a8b84d740b670a9f1df5148b824d441c63 (diff) | |
| parent | 8d70f7abf93689fcfa9f7bf9159b4511d475f74d (diff) | |
| download | yosys-eaf66037a59fc55d385d0bb4216b08fd565c05f1.tar.gz yosys-eaf66037a59fc55d385d0bb4216b08fd565c05f1.tar.bz2 yosys-eaf66037a59fc55d385d0bb4216b08fd565c05f1.zip | |
Merge pull request #2160 from whitequark/cxxrtl-fix-warning
cxxrtl: avoid unused variable warning for transparent $memrd ports
Diffstat (limited to 'backends/verilog')
0 files changed, 0 insertions, 0 deletions