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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-08 15:46:00 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-08 15:46:00 +0200 |
| commit | d97782b848bf5da4529e5b732b1ad06177539a93 (patch) | |
| tree | 5a8cdb84f9c311bd39782d8633d09768c1ba0aa8 /backends/verilog | |
| parent | 6a40e46a042ace384cabd78c7db967a271aadae7 (diff) | |
| download | yosys-d97782b848bf5da4529e5b732b1ad06177539a93.tar.gz yosys-d97782b848bf5da4529e5b732b1ad06177539a93.tar.bz2 yosys-d97782b848bf5da4529e5b732b1ad06177539a93.zip | |
Sort ctrl signals in fsm_extract
Diffstat (limited to 'backends/verilog')
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